32-bit ALU — RTL to GDSII

System Overview

The ALU operates on two 32-bit operands A and B under a 4-bit function select S[3:0] and carry-in Cin, producing a 32-bit result F and carry-out Cout; two serial inputs feed the shift operations. The design was written in two styles — a structural/hierarchical core built from 32 one-bit slices and a single-block behavioural core — carried through the full RTL-to-GDS flow, compared, and the smaller/faster hierarchical core selected for chip integration.

Functional Specification

The four select bits are partitioned in hardware: the upper pair S3 S2 chooses the operation class (arithmetic / logic / shift) at the output multiplexer, while the lower pair S1 S0 chooses the specific function. Cin distinguishes the two operations that share each arithmetic opcode.

Architecture — The 1-bit Slice

The whole design rests on one carefully built block. Each 1-bit slice runs an arithmetic circuit and a logic circuit in parallel (both controlled by S1 S0), and an output 4:1 multiplexer selects between the arithmetic result, the logic result, and the two shifted versions of A (controlled by S3 S2). This two-level select is what makes every slice identical — no bit position needs special-case control.

The arithmetic unit turns a single full adder into eight operations by multiplexing its second operand between 0, B, B̄ and 1. Subtraction reuses the same adder in two's-complement form — A − B = A + B̄ + 1 — so no dedicated subtractor is needed. The full adder shares its first XOR term between the sum and carry paths to minimise gate count:

assign sum_o  = a_i ^ b_i ^ cin_i;
assign cout_o = (a_i & b_i) | (cin_i & (a_i ^ b_i));

Bit-slice chaining → 32-bit datapath

Thirty-two identical slices are chained through a ripple carry: the external Cin enters slice 0, each slice passes its carry to the next, and the final carry becomes Cout. The same S3 S2 S1 S0 bus fans out to every slice. Shifts are handled once at the top level on the whole word.

The RTL-to-GDS Flow

Design intent is captured at the register-transfer level and progressively refined — through synthesis and physical implementation — into geometry, with functional and physical correctness checked at every hand-off. A failed signoff check (timing / DRC / connectivity) loops back as an ECO fix.

1. 1
   SpecificationFunction table and top-level I/O.
2. 2
   RTL designSynthesisable Verilog — structural and behavioural styles.
3. 3
   Functional simulationXcelium (SimVision) against exhaustive self-checking testbenches.
4. 4
   Logic synthesisGenus + gsclib045 → gate netlist, .sdc, area/power/timing reports.
5. 5
   Place & routeInnovus: floorplan, power, placement, routing, post-route timing.
6. 6
   Physical signoffDRC, connectivity and timing — loops back on any violation.
7. 7
   GDSII exportCore layout streamed out as alu_32bit.gds.
8. 8
   Chip integrationPad-frame assembly and full-chip stream-out in Virtuoso.

Choosing the slow, low-voltage, high-temperature corner (0.9 V, 125 °C) for setup analysis is deliberate — it is the worst case for cell delay, so timing that closes here closes across the operating range.

Synthesis Results & Core Selection

Three designs were carried through the flow: the 1-bit slice, the 32-bit hierarchical (structural) core, and a 32-bit behavioural core. The behavioural code writes each arithmetic operation as an independent +, so the synthesiser infers about twice the adder hardware (64 vs 32 full adders) and cannot share it — making it substantially larger.

Core area (µm²) — hierarchical vs behavioural

Area: the hierarchical core is 34.4% smaller thanks to operand-mux reuse of a single adder per slice. Speed: the two are effectively tied (9.72 vs 9.83 ns) — both limited by a 32-stage ripple-carry chain that dominates the critical path (≈186 ps per adder stage). Power: the behavioural design draws marginally less total power because its redundant adders are not all active for a given operation, a small effect that does not offset the area gap.

Key design decisions

1. 1
   Bit-slice architectureOne verified 1-bit cell tiled 32× — modularity, reuse, and low verification effort.
2. 2
   Single shared adder per sliceAdd / subtract / increment / decrement by multiplexing the adder's second operand (0, B, B̄, 1); two's-complement subtraction.
3. 3
   Two-level selectS3 S2 picks the operation class at the output mux; S1 S0 picks the specific function — every slice stays identical.
4. 4
   Structural over behaviouralChosen for 34.4% smaller area through adder sharing, at equal speed.
5. 5
   Worst-case corner signoffslow_vdd1v0 / PVT_0P9V_125C so timing closure is conservative across the operating range.

Place & Route

The synthesised netlist is imported into Innovus, floorplanned, and given power rails (VDD/VSS), placement and routing. The 32-bit hierarchical core places into a die of roughly 50.8 × 44.5 µm, with the ripple-carry adder chain forming the dominant routed path.

Physical Verification

Two signoff checks confirm the layout is manufacturable and matches the netlist. Both pass cleanly on every design: the geometry obeys all 45 nm design rules, and every net is fully connected with no opens or shorts.

Verification & Test Flow

Because every block is small, verification uses exhaustive rather than random vectors. Each sub-block (4:1 mux, arithmetic circuit, logic circuit) is checked in Xcelium with a self-checking testbench that sweeps all input combinations, then the assembled slice is verified against the full functional table, and finally the 32-bit cores are simulated with wide operands across every operation class.

a = 1'b1; b = 1'b0;
sel = 4'b0000; cin = 1'b0; #5;  // F = A
sel = 4'b0001; cin = 1'b0; #5;  // F = A + B
sel = 4'b0010; cin = 1'b1; #5;  // F = A - B  (two's complement)
sel = 4'b0100;             #5;  // F = A & B
sel = 4'b1000;             #5;  // F = shr A
$finish;

Shifts are handled once at the top level rather than inside each slice, mirroring the per-slice output mux but applied to the whole word:

assign f_o = (sel[3:2] == 2'b10) ? (a >> 1) :
             (sel[3:2] == 2'b11) ? (a << 1) : ripple_result;
assign cout_o = (sel[3:2] == 2'b10 || sel[3:2] == 2'b11) ? 1'b0 : carry[32];

A representative verification vector set — the 4:1 multiplexer, exercised across both complementary operand sets:

Pad Frame & Chip Integration

The selected core is streamed out as GDSII and placed inside a 104-signal pad ring — 26 pads on each of the four edges — in Virtuoso. Grouping the buses by edge keeps the core-to-pad routing short: operands A/B enter from the top and left, the result F leaves from the right and bottom, and the controls sit together on the bottom edge. Corner pads carry VDD/VSS.

Status: the core is placed and a subset of I/O nets are wired; the pad plan, pin assignment and routing methodology are fully defined — completing the remaining pad connections and re-running full-chip DRC/LVS is the final step to a tape-out-ready layout.

Results & Future Work