Wearable ECG Holter Monitor
Wearable ESP32 + AD8232 node that streams real-time ECG over Wi-Fi through an 8-stage DSP pipeline to a live browser dashboard.
- ESP32
- Django Channels
- SciPy
- Chart.js
About
Who I am
I'm Salwan Aldhahab, a Computer Engineer who gets fired up by building across every layer of the stack.
I thrive in the space between transistors and applications, circuits and code — chasing problems wherever they lead, whether the answer lives in hardware or software.
What excites me most is co-design: that spark when a firmware choice reshapes the silicon, and a silicon constraint rewrites the code. It's where I do my best work.
I hold a Specialized Honours BEng in Computer Engineering from York University — and I'm just getting started. To me, engineering isn't about what you already know; it's about how fast and how eagerly you learn what you don't.
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Specialized Honours BEng
Computer Engineering · York University
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Hardware
RTL · FPGA · ASIC · embedded
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Software
Full-stack · DSP · systems
Projects
Recent work
32-bit RISC-V Processor (UART + VGA)
Custom RV32I CPU on the DE10-Lite FPGA — instructions streamed over UART through a 5-stage pipeline with valid/flush handshakes, register state on VGA.
- Verilog
- RISC-V
- FPGA
- VGA
Pipelined RV32I RISC-V Core
Five-stage RV32I core in SystemVerilog with a forwarding/stall/flush hazard unit — verified across the full rv32-bmarks suite (64/64 pass).
- SystemVerilog
- RV32I
- Pipeline
- Verification
32-bit ALU — RTL to GDSII
Complete Cadence ASIC flow for a bit-slice 32-bit ALU on GPDK045 45 nm — RTL, synthesis, place-and-route, signoff and pad-frame integration.
- Verilog
- Cadence
- 45 nm
- ASIC
YUPlanner
Three-tier academic planner — React SPA + Spring Boot REST API + MySQL — with course scheduling, professor ratings and PDF export across student/professor/advisor roles.
- React
- Spring Boot
- MySQL
- REST
Contact